I/O pull-down devices have regularly been used to protect I/O logic circuits from electrostatic discharge (ESD). One such I/O pull-down device 100 is shown in FIG. 1. Device 100 comprises a P-well or P-type substrate 110 having P+ taps or contacts 120, a polysilicon gate 130 on the substrate and insulated therefrom by gate oxide 140, heavily doped N-type source and drain regions 150, 160, and N-type lightly doped drain (LDD) regions 170, 180 extending toward each other in the substrate from the source and drain regions. A parasitic NPN bipolar transistor is formed in this device in which the source and drain regions 150, 160 are the emitter and collector of the transistor and the P-well or substrate 110 is the base. The structure of a typical I/O logic circuit is similar to that of device 100 and is typically formed in the same integrated circuit as I/O pull-down device 100.
As device dimensions get smaller and smaller, it becomes increasingly more difficult to use such I/O pull-down devices to protect I/O logic circuits. The turn-on-voltage for the parasitic bipolar device in both the I/O pull-down circuit and the I/O logic circuit increases as the spacing between the P+ taps and the N+ diffusion decreases. In a practical design, a group of I/O transistors share common P+ taps for minimizing the circuit area; and the spacing between the farthest logic transistor and its P+ taps can be larger than that between the I/O pull-down transistor and its P+ taps. As a result, the parasitic bipolar device for the logic transistor can trigger at a lower voltage than that for the I/O pull-down transistor. This can occur at the 90 nm node and nodes beyond that.
Various methods are used for reducing the trigger voltage of the I/O pull-down transistor. In U.S. Pat. No. 6,882,009 of M. Ker et al., P-type pocket implants are used next to the source/drain regions. However, since the P-type pocket implants are used throughout the circuit, this reduces the trigger voltage of both the pull-down transistors and the logic transistors. As a result, the I/O pull-down transistor may not be able to protect the I/O logic circuit. In addition, the P-type pocket implant can degrade the transistor performance by increasing its junction capacitance, and thereby reducing its speed, and can increase the transistor leakage. In M. Ker et al., “ESD Implantation for On-Chip ESD Protection with Layout Consideration in 0.18 um Salicided CMOS Technology,” IEEE Transactions on Semiconductor Manufacturing, Vol. 18, No. 2, pp. 328-337 (May 2005), a P-type ESD implant is located vertically under the source-drain area. This, however, significantly increases the junction capacitance and affects the transistor performance. It also increases the transistor leakage.